Hardware Design of Dynamic Time Warping Algorithm based on FPGA in Verilog

The Dynamic Time Warping (DTW) algorithm is a software technique to quantify the diversity between two time varying sequences. In spite of its computational complexity, it is often used in speech recognition systems. In this work, hardware implementation of DTW modeled in VERILOG Hardware Description Language (HDL) has been done, with an aim to use it as an independent unit or as a co-processor in large embedded systems. The target device used for synthesis is xc3s400-4pq208 in Xilinx. Simulations were performed in ModelSim. Hardware utilization analysis is provided to show its efficacy in warping a sequence in non linear fashion. Index Terms —dynamic time warping, verilog, time sequence data, Field Programmable Gate Array (FPGA), Look Up Tables (LUTs), Application Specific Integrated Circuits (ASICs)